1. Field of the Invention
Exemplary embodiments of the present invention relate to a semiconductor design technique, and more particularly, to a semiconductor integrated circuit having a three dimensional (3D) stack package structure.
2. Description of the Related Art
Technology for packaging a semiconductor integrated circuit has been developed to satisfy the need for reliable, small-sized packaging. Particularly, various technologies regarding stack packaging have developed recently in response to the demand for the miniaturization and high performance of electrical/electronic devices.
A ‘stack package’ in the semiconductor technology field refers to a device that has two or more chips or packages stacked in a vertical direction. By implementing a stack package, a semiconductor memory device may have a memory capacity that has more than twice the memory capacity achieved through a typical semiconductor integration process. Because of the advantages of the stack package with respect to memory capacity, package density, and package size, research and development of the stack package has accelerated.
A stack package may be formed by stacking semiconductor chips, and then packaging the stacked semiconductor chips. Alternatively, the stack package may be formed by first packaging semiconductor chips, and then stacking the packaged semiconductor chips. The respective semiconductor chips in the stack package are electrically connected to each other through a metal wire or a through chip via. The stack package using a through chip via has a structure such that semiconductor chips are physically and electrically connected to each other in a vertical direction by a through chip via formed within a semiconductor substrate.
FIG. 1 is a perspective view illustrating a semiconductor chip including a through chip via.
Referring to FIG. 1, a stack package C is formed by forming a hole within a semiconductor chip A, filling the hole with a metal, e.g., Cu, having good conductivity to form a through chip via B, and then stacking another semiconductor chip A on top of the semiconductor chip A having the through chip via B. A plurality of stacked semiconductor chips A is packaged in a package substrate such as a printed circuit board (PCB) to form a semiconductor integrated circuit. Generally, the semiconductor integrated circuit is called a three dimensional (3D) stack package semiconductor integrated circuit.
FIG. 2 is a cross-sectional view showing the 3D stack package semiconductor integrated circuit. For the sake of convenience, the 3D stack package semiconductor integrated circuit including only four semiconductor chips stacked on a surface of a package substrate is illustrated and described.
Referring to FIG. 2, a 3D stack package semiconductor integrated circuit (hereinafter referred to “a semiconductor integrated circuit”) 100 includes a package substrate 110, first to fourth semiconductor chips 120, 130, 140 and 150, first to fourth through chip vias 120A, 130A, 140A and 150A, and first to third connection pads 160, 170, and 180. The first to fourth semiconductor chips 120, 130, 140 and 150 are stacked on a top surface of the package substrate 110 in a vertical direction. The first to fourth through chip vias 120A, 130A, 140A and 150A are provided to the first to fourth semiconductor chips 120, 130, 140 and 150, respectively. The first connection pad 160 is formed between the first semiconductor chip 120 and the second semiconductor chip 130 to connect the first through chip via 120A to the second through chip via 130A. The second connection pad 170 is formed between the second semiconductor chip 130 and the third semiconductor chip 140 to connect the second through chip via 130A to the third through chip via 140A. The third connection pad 180 is formed between the third semiconductor chip 140 and the fourth semiconductor chip 150 to connect the third through chip via 140A to the fourth through chip via 150A.
The package substrate 110 electrically connects an external controller (not shown) to the first semiconductor chip 120. The package substrate 110 includes an external connection terminal 102 on a bottom surface of the package substrate 110 for providing an electrical connection for connecting to the external controller. Also, the package substrate 110 includes an internal connection terminal 104 on a top surface of the package substrate 110 for providing an electrical connection to the first to fourth semiconductor chips 120, 130, 140 and 150. As such, the package substrate 110 interfaces signals and power with the external controller through the external connection terminal 102 to transfer the received signals and power to the first semiconductor chip 120, and transfer signals received from the first to fourth semiconductor chips 120, 130, 140 and 150 to the external controller through the external connection terminal 102. For example, a printed circuit board (PCB) may be used as the package substrate 110.
The first to fourth semiconductor chips 120, 130, 140 and 150 perform a certain operation in response to signals and power provided from the package substrate 110. For example, the first to fourth semiconductor chips 120, 130, 140 and 150 store data provided from the external controller, or provide stored data to the external controller. A P-type substrate doped by a P-type impurity may be used as the first to fourth semiconductor chips 120, 130, 140 and 150. At this time, several circuits for certain operations are disposed on an active layer formed on a top surface of the P-type substrate.
The first to fourth through chip vias 120A, 130A, 140A and 150A interface various signals and power, and are implemented by using a metal with good conductivity, e.g., Cu, Al, etc. The first to fourth through chip vias 120A, 130A, 140A and 150A may be through silicon vias (TSV). Hereinafter, for the sake of convenience, the first to fourth through chip vias 120A, 130A, 140A and 150A for interfacing power (e.g., a power supply voltage signals, a ground voltage supply signal, etc.) will be described.
The first to third connection pads 160, 170 and 180 may include a bump pad, respectively.
Hereinafter, the semiconductor integrated circuit 100 will be described in detail. The semiconductor integrate circuit 100 has a similar connection configuration and a similar structure of a semiconductor chip—a connection pad—a semiconductor chip in sequence. Thus, for the sake of convenience, only portion W1 of the semiconductor integrated circuit 100 will be described.
In the enlarged portion W1, the third semiconductor chip 140 includes a plurality of third through chip vias 140A, and the fourth semiconductor chip 150 includes a plurality of fourth through chip vias 150A. A plurality of third connection pads 180 is disposed between the third semiconductor chip 140 and the fourth semiconductor chip 150 to connect the third through chip vias 140A to the respective fourth through chip vias 150A. A plurality of third isolation layers 140B encompasses the respective surroundings of the plurality of third through chip vias 140A, respectively. A plurality of fourth isolation layers 150B encompasses the respective surroundings of the plurality of fourth through chip vias 150A, respectively. The plurality of third isolation layers 140B prevents an electrical connection between the plurality of third through chip vias 140A and the third semiconductor chip 140. The plurality of fourth isolation layers 150B prevents an electrical connection between the plurality of fourth through chip vias 150A and the fourth semiconductor chip 150. Openings S are formed between the third semiconductor chip 140 and the fourth semiconductor chip 150, due to the plurality of third connection pads 180. Openings S are conventionally filled with polymer.
As described above, the semiconductor integrated circuit 100 is provided with power through the first to fourth through chip vias 120A, 130A, 140A and 150A. Thus, power consumption and signal delay can be reduced and operation performance can be increased due to the improved bandwidth.
However, the semiconductor integrated circuit 100 may have disadvantages as discussed below.
The first to fourth through chip vias 120A, 130A, 140A and 150A should be provided to the first to fourth semiconductor chips 120, 130, 140 and 150, respectively. As a result, the first to fourth semiconductor chips 120, 130, 140 and 150 may increase in size and such an increment in size may not be desirable in view of the trend towards high integration in a semiconductor integrated circuit. Coping with this situation, unnecessary circuits among various circuits disposed on active layers of the first to fourth semiconductor chips 120, 130, 140 and 150 may be removed. For example, a reservoir capacitor included in a peripheral region of the semiconductor chip can be removed to reduce the size of the semiconductor chip. However, this scheme makes a power provided through the first to fourth through chip vias 120A, 130A, 140A and 150A unstable. Furthermore, it may cause malfunction of the first to fourth semiconductor chips 120, 130, 140 and 150 and affect operational reliability of the semiconductor integrated circuit 100.